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asahi kasei [ak4394] m0081-e-00 1999/11 - 1 - general description the ak4394 is a high performance stereo dac for the 192khz sampling mode of dvd-audio including a 24bit digital filter. the ak4394 introduces the advanced multi-bit system for ds modulator. this new architecture achieves the wider dynamic range, while keeping much the same superior distortion characteristics as conventional single-bit way. in the ak4394, the analog outputs are filtered in the analog domain by switched-capacitor filter(scf) with high tolerance to clock jitter. the analog outputs are full differential output, so the device is suitable for hi-end applications. the digital i/f can correspond to ttl levels, so it is easy to i/f with 3.3v logic ic. features 128x oversampling sampling rate up to 192khz 24bit 8x digital filter (slow-roll-off option) ripple: 0.005db, attenuation: 75db high tolerance to clock jitter low distortion differential output digital de-emphasis for 32, 44.1, 48 & 96khz sampling soft mute thd+n: -100db dr, s/n: 120db i/f format : msb justified, 16/20/24bit lsb justified, i 2 s master clock: normal speed: 256fs, 384fs, 512fs or 768fs double speed: 128fs, 192fs, 256fs or 384fs quad speed: 128fs or 192fs power supply: 5v 5% ttl level digital i/f small package: 28pin vsop pin compatible with ak4393 dem1 lrck bick sdat a audio data interface dem0 dvdd csn av d d aoutr+ 8x interpolator scf ds modulator aoutr- scf de-emphasis soft mute control register clock divider de-emphasis control pdn cclk cdti p/s mclk cks0 cks1 cks2 vrefh vrefl aoutl+ aoutl- vcom bvss av s s dvss dif2 dif1 dif0 smute dfs0 dzfl dzfr de-emphasis soft mute 8x interpolator ds modulator advanced multi-bit 192khz 24-bit ds dac ak4394
asahi kasei [ak4394] m0081-e-00 1999/11 - 2 - n ordering guide AK4394VF -40 ~ +85 c 28pin vsop (0.65mm pitch) akd4394 evaluation board n n n n pin layout 6 5 4 3 2 1 dvss dvdd pdn mclk bick sdata lrck 7 smute/csn 8 cks2/dzfr cks1 cks0/dzfl p/s vcom aoutl + aoutl- aoutr+ top view 10 9 dfs0 dem0/cclk dem1/cdti 11 dif0 12 aoutr- avss avdd vrefh 23 24 25 26 27 28 22 21 19 20 18 17 13 14 16 15 dif1 dif2 vrefl bvss n n n n pin compatibility with ak4393 ak4393 ak4394 fs (max) 108khz 216khz slow roll-off filter not available available zero detection not available available dvdd 3~5.25v 4.75~5.25v pin #26 (serial mode) cks0 dzfl pin #28 (serial mode) cks2 dzfr control register : 01h d4 0 dfs1 control register : 01h d5 0 slow control register : 01h d6 0 dzfm control register : 01h d7 0 dzfe
asahi kasei [ak4394] m0081-e-00 1999/11 - 3 - pin/function no. pin name i/o function 1 dvss - digital ground pin 2 dvdd - digital power supply pin, 5.0v 3 mclk i master clock input pin 4 pdn i power-down mode pin when at l, the ak4394 is in power-down mode and is held in reset. the ak4394 should always be reset upon power-up. 5 bick i audio serial data clock pin the clock of 64fs or more than is recommended to be input on this pin. 6 sdata i audio serial data input pin 2s complement msb-first data is input on this pin. 7 lrck i l/r clock pin smute i soft mute pin in parallel mode when this pin goes "h", soft mute cycle is initiated. when returning l, the output mute releases. 8 csn i chip select pin in serial mode 9 dfs0 i double speed sampling mode pin (internal pull-down pin) l: normal speed , h: double speed dem0 i de-emphasis enable pin in parallel mode 10 cclk i control data clock pin in serial mode dem1 i de-emphasis enable pin in parallel mode 11 cdti i control data input pin in serial mode 12 dif0 i digital input format pin 13 dif1 i digital input format pin 14 dif2 i digital input format pin 15 bvss - substrate ground pin, 0v 16 vrefl i low level voltage reference input pin 17 vrefh i high level voltage reference input pin 18 avdd - analog power supply pin, 5.0v 19 avss - analog ground pin, 0v 20 aoutr- o rch negative analog output pin 21 aoutr+ o rch positive analog output pin 22 aoutl- o lch negative analog output pin 23 aoutl+ o lch positive analog output pin 24 vcom o common voltage output pin, 2.6v 25 p/s i parallel/serial select pin (internal pull-up pin) l: serial control mode, h: parallel control mode cks0 i master clock select pin in parallel mode 26 dzfl o lch zero input detect pin in serial mode 27 cks1 i master clock select pin cks2 i master clock select pin in parallel mode 28 dzfr o rch zero input detect pin in serial mode note: all input pins except internal pull-up/down pins should not be left floating.
asahi kasei [ak4394] m0081-e-00 1999/11 - 4 - absolute maximum ratings (avss, bvss, dvss = 0v; note 1) parameter symbol min max units power supplies: analog digital | bvss-dvss | (note 2) avdd dvdd d gnd -0.3 -0.3 - 6.0 6.0 0.3 v v v input current , any pin except supplies iin - 10 ma input voltage vind -0.3 dvdd+0.3 v ambient operating temperature ta -40 85 c storage temperature tstg -65 150 c notes: 1. all voltages with respect to ground. 2. avss, bvss and dvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, bvss, dvss=0v; note 1) parameter symbol min typ max units power supplies: (note 3) analog digital avdd dvdd 4.75 4.75 5.0 5.0 5.25 5.25 v v voltage reference (note 4) h voltage reference l voltage reference vrefh-vrefl vrefh vrefl d vref avdd-0.5 avss 3.0 - - - avdd - avdd v v v notes: 3. the power up sequence between avdd and dvdd is not critical. 4. analog output voltage scales with the voltage of (vrefh-vrefl). aout (typ.@0db) = (aout+) - (aout-) = 2.4vpp(vrefh-vrefl)/5. * akm assumes no responsibility for the usage beyond the conditions in this data sheet.
asahi kasei [ak4394] m0081-e-00 1999/11 - 5 - analog characteristics (ta = 25 c; avdd, dvdd = 5v; avss, bvss, dvss = 0v, vrefh = avdd, vrefl = avss; fs = 44.1khz; bick = 64fs; signal frequency = 1khz; 24bit input data; measurement bandwidth = 20hz~20khz; r l 3 600 w ; external circuit: figure 12; unless otherwise specified) parameter min typ max units resolution 24 bits dynamic characteristics (note 5) fs=44.1khz bw=20khz 0dbfs -60dbfs -100 -53 -90 - db db fs=96khz bw=40khz 0dbfs -60dbfs -97 -51 -87 - db db thd+n fs=192khz bw=40khz 0dbfs -60dbfs -97 -51 - - db db dynamic range (-60dbfs with a-weighted) (note 6) (note 7) 112 - 117 120 db db s/n (a-weighted (note 8) (note 7) 112 - 117 120 db db interchannel isolation (1khz) 100 120 db dc accuracy interchannel gain mismatch 0.15 0.3 db gain drift (note 9) 20 - ppm/ c output voltage (note 10) 2.25 2.4 2.55 vpp load resistance (note 11) 600 w output current 3.5 ma power supplies power supply current normal operation (pdn = h) avdd dvdd(fs=44.1khz) dvdd(fs=96khz) dvdd(fs=192khz) avdd + dvdd 60 5 8 12 - - - - 90 ma ma ma ma ma power-down mode (pdn = l) avdd + dvdd (note 12) 10 100 a power supply rejection (note 13) 50 db notes: 5. at 44.1khz, measured by audio precision, system two. averaging mode. at 96khz and 192khz, measured by rohde & schwarz, upd. averaging mode. refer to the eva board manual. 6. 101db at 16bit data and 116db at 20bit data. 7. by figure13. external lpf circuit example 2. 8. s/n does not depend on input bit length. 9. the voltage on (vrefh-vrefl) is held +5v externally. 10. full-scale voltage(0db). output voltage scales with the voltage of (vrefh-vrefl). aout (typ.@0db) = (aout+) - (aout-) = 2.4vpp(vrefh-vrefl)/5. 11. for ac-load. 1k w for dc-load. 12. in the power-down mode. p/s = dvdd, and all other digital input pins including clock pins (mclk, bick and lrck) are held dvss. 13. psr is applied to avdd, dvdd with 1khz, 100mvpp. vrefh pin is held +5v.
asahi kasei [ak4394] m0081-e-00 1999/11 - 6 - sharp roll-off filter characteristics (fs = 44.1khz) (ta = 25 c; avdd, dvdd = 4.75~5.25v; fs = 44.1khz; normal speed mode; dem = off; slow = 0) parameter symbol min typ max units digital filter passband 0.01db (note 14) -6.0db pb 0 - 22.05 20.0 - khz khz stopband (note 14) sb 24.1 khz passband ripple pr 0.005 db stopband attenuation sa 75 db group delay (note 15) gd - 28 - 1/fs digital filter + scf frequency response 0 ~ 20.0khz - 0.2 - db note: 14. the passband and stopband frequencies scale with fs. for example, pb = 0.4535fs (@ 0.01db), sb = 0.546fs. 15. the calculating delay time which occurred by digital filtering. this time is from setting the 16/20/24bit data of both channels to input register to the output of analog signal. sharp roll-off filter characteristics (fs = 96khz) (ta = 25 c; avdd, dvdd = 4.75~5.25v; fs = 96khz; double speed mode; dem = off; slow = 0) parameter symbol min typ max units digital filter passband 0.01db (note 14) -6.0db pb 0 - 48.0 43.5 - khz khz stopband (note 14) sb 52.5 khz passband ripple pr 0.005 db stopband attenuation sa 75 db group delay (note 15) gd - 28 - 1/fs digital filter + scf frequency response 0 ~ 40.0khz - 0.3 - db sharp roll-off filter characteristics (fs = 192khz) (ta = 25 c; avdd, dvdd = 4.75~5.25v; fs = 192khz; quad speed mode; dem = off; slow = 0) parameter symbol min typ max units digital filter passband 0.01db (note 14) -6.0db pb 0 - 96.0 87.0 - khz khz stopband (note 14) sb 105 khz passband ripple pr 0.005 db stopband attenuation sa 75 db group delay (note 15) gd - 28 - 1/fs digital filter + scf frequency response 0 ~ 80.0khz - +0/-1 - db
asahi kasei [ak4394] m0081-e-00 1999/11 - 7 - slow roll-off filter characteristics (fs = 44.1khz) (ta = 25 c; avdd, dvdd = 4.75~5.25v; fs = 44.1khz; normal speed mode; dem = off; slow = 1) parameter symbol min typ max units digital filter passband 0.04db (note 16) -3.0db pb 0 - 18.2 8.1 - khz khz stopband (note 16) sb 39.2 khz passband ripple pr 0.005 db stopband attenuation sa 72 db group delay (note 15) gd - 28 - 1/fs digital filter + scf frequency response 0 ~ 20.0khz - +0/-5 - db note: 16. the passband and stopband frequencies scale with fs. for example, pb = 0.185fs (@ 0.04db), sb = 0.888fs. slow roll-off filter characteristics (fs = 96khz) (ta = 25 c; avdd, dvdd = 4.75~5.25v; fs = 96khz; double speed mode; dem = off; slow = 1) parameter symbol min typ max units digital filter passband 0.04db (note 16) -3.0db pb 0 - 39.6 17.7 - khz khz stopband (note 16) sb 85.3 khz passband ripple pr 0.005 db stopband attenuation sa 72 db group delay (note 15) gd - 28 - 1/fs digital filter + scf frequency response 0 ~ 40.0khz - +0/-4 - db slow roll-off filter characteristics (fs = 192khz) (ta = 25 c; avdd, dvdd = 4.75~5.25v; fs = 192khz; quad speed mode; dem = off; slow = 1) parameter symbol min typ max units digital filter passband 0.04db (note 16) -3.0db pb 0 - 79.1 35.5 - khz khz stopband (note 16) sb 171 khz passband ripple pr 0.005 db stopband attenuation sa 72 db group delay (note 15) gd - 28 - 1/fs digital filter + scf frequency response 0 ~ 80.0khz - +0/-5 - db
asahi kasei [ak4394] m0081-e-00 1999/11 - 8 - dc characteristics (ta = 25 c; avdd, dvdd = 4.75~5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v high-level output voltage (iout = -100 m a) low-level output voltage (iout = 100 m a) voh vol dvdd-0.5 - - - - 0.5 v v input leakage current (note 17) iin - - 10 a note: 17. dfs0, p/s pins have internal pull-down or pull-up devices, nominally 100k w . switching characteristics (ta = 25 c; avdd, dvdd = 4.75~5.25v; c l = 20pf) parameter symbol min typ max units master clock timing frequency duty cycle fclk dclk 7.7 40 41.472 60 mhz % lrck frequency (note 18) normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 30 60 120 45 54 108 216 55 khz khz khz % serial interface timing bick period normal speed mode double speed mode quad speed mode bick pulse width low pulse width high bick - to lrck edge (note 19) lrck edge to bick - (note 19) sdata hold time sdata setup time tbck tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fs 1/64fs 1/64fs 30 30 20 20 20 20 ns ns ns ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn high time csn to cclk - cclk - to csn - tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 50 50 150 50 50 ns ns ns ns ns ns ns ns reset timing pdn pulse width (note 20) tpd 150 ns notes: 18. when the normal/double/quad speed modes are switched, ak4394 should be reset by pdn pin or rstn bit. 19. bick rising edge must not occur at the same time as lrck edge. 20. the ak4394 can be reset by bringing pdn l to h. when the states of cks2-0 or dfs1-0 change, the ak4394 should be reset by pdn pin or rstn bit.
asahi kasei [ak4394] m0081-e-00 1999/11 - 9 - n timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdata vil tsdh vih vil tblr audio interface timing
asahi kasei [ak4394] m0081-e-00 1999/11 - 10 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing tpd vil pdn power-down timing
asahi kasei [ak4394] m0081-e-00 1999/11 - 11 - operation overview n system clock the external clocks, which are required to operate the ak4394, are mclk, lrck and bick. the master clock (mclk) should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. the sampling speed is set by dfs0/1(table 1). the sampling rate (lrck), cks0/1/2 and dfs0/1 determine the frequency of mclk (table 2). in parallel mode, since dfs1 is always 0, the quad speed mode can not be available. all external clocks (mclk, bick and lrck) should always be present whenever the ak4394 is in normal operation mode (pd = h). if these clocks are not provided, the ak4394 may draw excess current because the device utilizes dynamic refreshed logic internally. if the external clocks are not present, the ak4394 should be in the power-down mode (pdn = l) or in the reset mode (rstn = 0). after exiting reset at power-up etc., the ak4394 is in power-down mode until mclk and lrck are input. dfs1 dfs0 sampling rate (fs) 0 0 normal speed mode 30khz~54khz default 0 1 double speed mode 60khz~108khz 1 0 quad speed mode 120khz~216khz table 1. sampling speed mode cks2 cks1 cks0 normal double quad 0 0 0 0 256fs 128fs n/a default 1 0 0 1 256fs 256fs n/a 2 0 1 0 384fs 192fs n/a 3 0 1 1 384fs 384fs n/a 4 1 0 0 512fs 256fs 128fs 5 1 0 1 512fs n/a n/a 6 1 1 0 768fs 384fs 192fs 7 1 1 1 768fs n/a n/a table 2. system clocks note: the master clock at quad speed supports only 128fs or 192fs. lrck mclk bick fs 256fs 384fs 512fs 768fs 64fs 32.0khz 8.1920mhz 12.2880mhz 16.3840mhz 24.5760mhz 2.0480mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 2.8224mhz 48.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 3.0720mhz table 3. system clock example (normal speed mode)
asahi kasei [ak4394] m0081-e-00 1999/11 - 12 - lrck mclk bick fs 128fs 192fs 256fs 384fs 64fs 88.2khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 5.6448mhz 96.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 6.1440mhz table 4. system clock example (double speed mode) lrck mclk bick fs 128fs 192fs 64fs 176.4khz 22.5792mhz 33.8688mhz 11.2896mhz 192.0khz 24.5760mhz 36.8640mhz 12.2880mhz table 5. system clock example (quad speed mode) n n n n audio serial interface format data is shifted in via the sdata pin using bick and lrck inputs. five data formats are supported and selected by the dif0-2 as shown in table 6. in all formats the serial data is msb-first, 2's compliment format and is latched on the rising edge of bick. mode 2 can be used for 20 and 16 msb justified formats by zeroing the unused lsbs. mode dif2 dif1 dif0 mode bick figure 0 0 0 0 0: 16bit lsb justified 3 32fs figure 1 1 0 0 1 1: 20bit lsb justified 3 40fs figure 2 2 0 1 0 2: 24bit msb justified 3 48fs figure 3 30113: i 2 s compatible 3 48fs figure 4 4 1 0 0 4: 24bit lsb justified 3 48fs figure 2 table 6. audio data formats sdata bick lrck sdata 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3210 1514 ( 32fs ) ( 64fs ) 014 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 dont care dont care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 1. mode 0 timing
asahi kasei [ak4394] m0081-e-00 1999/11 - 13 - sdata lrck bick ( 64fs ) 09 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 dont care dont care 19:msb, 0:lsb sdata mode 4 23:msb, 0:lsb 20 19 0 20 19 0 dont care dont care 22 21 22 21 lch data rch data 8 23 23 8 figure 2. mode 1,4 timing lrck bick ( 64fs ) sdata 022 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 dont care 23 lch data rch data 23 30 22 224 23 30 22 1 0 dont care 23 22 23 figure 3. mode 2 timing lrck bick ( 64fs ) sdata 03 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 dont care 23 lch data rch data 23 25 3 224 23 25 22 1 0 dont care 23 23 figure 4. mode 3 timing
asahi kasei [ak4394] m0081-e-00 1999/11 - 14 - n n n n de-emphasis filter a digital de-emphasis filter is available for 32, 44.1, 48 or 96khz sampling rates (tc = 50/15s) and is enabled or disabled with the dem0, dem1 and dfs0 input pins. in case of quad mode (dfs1 = 1), the digital de-emphasis filter is always off. dem1 dem0 dfs0 mode 0 0 0 44.1khz default 010off 1 0 0 48khz 1 1 0 32khz 001off 011off 1 0 1 96khz 111off table 7. de-emphasis filter control (dfs1 = 0)
asahi kasei [ak4394] m0081-e-00 1999/11 - 15 - n zero detection the ak4394 has channel-independent zeros detect function. when the input data at each channel is continuously zeros for 8192 lrck cycles, dzf pin of each channel goes to h. dzf pin of each channel immediately goes to l if input data of each channel is not zero after going dzf h. if rstn bit is 0, dzf pins of both channels go to h. dzf pin of both channels go to l at 2~3/fs after rstn bit returns to 1. if dzfm bit is set to 1, dzf pins of both channels go to h only when the input data at both channels are continuously zeros for 8192 lrck cycles. zero detect function can be disabled by dzfe bit. in this case, dzf pins of both channels are always l. n soft mute operation soft mute operation is performed at digital domain. when smute goes to h, the output signal is attenuated by - during 1024 lrck cycles. when smute is returned to l, the mute is cancelled and the output attenuation gradually changes to 0db during 1024 lrck cycles. if the soft mute is cancelled within 1024 lrck cycles after starting the operation, the attenuation is discontinued and returned to 0db. the soft mute is effective for changing the signal source without stopping the signal transmission. smute attenuation dzf 1024/fs 0db - aout 1024/fs 8192/fs gd gd (1) (2) (3) (4) notes: (1) the output signal is attenuated by - during 1024 lrck cycles (1024/fs). (2) analog output corresponding to digital input has the group delay (gd). (3) if the soft mute is cancelled within 1024 lrck cycles, the attenuation is discontinued and returned to 0db. (4) when the input data at each channel is continuously zeros for 8192 lrck cycles, dzf pin of each channel goes to h. dzf pin immediately goes to l if input data are not zero after going dzf h. figure 5. soft mute and zero detection
asahi kasei [ak4394] m0081-e-00 1999/11 - 16 - n system reset the ak4394 should be reset once by bringing pdn = l upon power-up. the ak4394 is powered up and the internal timing starts clocking by lrck - after exiting reset and power down state by mclk. the ak4394 is in the power-down mode until mclk and lrck are input. n power-down the ak4394 is placed in the power-down mode by bringing pdn pin l and the anlog outputs are floating (hi-z). figure 6 shows a n example of the system timing at the power-down and power-up. normal operation internal state pdn power-down normal operation gd gd 0 data d/a out (analog) d/a in (digital) clock in mclk, lrck, bick (1) (3) (6) dzfl/dzfr external mute (5) (3) (1) mute on (2) (4) dont care notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs are floating (hi -z) at the power-down mode. (3) click noise occurs at the edge of pdn signal. this noise is output even if 0 data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the power-down mode (pdn = l). (5) please mute the analog output externally if the click noise (3) influences system application. the timing example is shown in this figure. (6) dzf pins are l in the power-down mode (pdn = l). figure 6. power-down/up sequence example
asahi kasei [ak4394] m0081-e-00 1999/11 - 17 - n n n n reset function when rstn = 0, the ak4394s digital section is powered down but the internal register values are not initialized. the analog outputs go to vcom voltage and dzf pins of both channels go to h. figure 7 shows the example of reset by rstn bit. internal state rstn bit digital block power-down normal operation gd gd 0 data d/a out (analog) d/a in (digital) clock in mclk,lrck,bick (1) (3) dzfl/dzfr (3) (1) (2) normal operation 2/fs(5) internal rstn bit 2~3/fs (6) 3~4/fs (6) dont care (4) notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs go to vcom voltage. (3) click noise occurs at the edges( - ) of the internal timing of rstn bit. this noise is output even if 0 data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the reset mode (rstn = l). (5) dzf pins go to h when the rstn bit becomes 0, and go to l at 2/fs after rstn bit becomes 1. (6) there is a delay, 3~4/fs from rstn bit 0 to the internal rstn bit 0, and 2~3/fs from rstn bit 1 to the internal rstn 1. figure 7. reset sequence example
asahi kasei [ak4394] m0081-e-00 1999/11 - 18 - n mode control interface pins (parallel control mode) or registers (serial control mode) can control each functions of the ak4394. for dif0/1/2, cks1 and dfs0, the setting of pin and register are ored internally. so, even serial control mode, these functions can be also controlled by pin setting. the serial control interface is enabled by the p/s pin = l. in this mode, pin setting must be all l. internal registers may be written by 3-wire p interface pins: csn, cclk and cdti. the data on this interface consists of chip address (2bits, c1/0; fixed to 01), read/write (1bit; fixed to 1), register address (msb first, 5bits) and control data (msb first, 8bits). the ak4394 latches the data on the rising edge of cclk, so data should be clocked in on the falling edge. the writing of data becomes valid by csn - . the clock speed of cclk is 5mhz(max). the csn and cclk must be fixed to h when the register does not be accessed. function parallel mode serial mode double speed o o quad speed x o de-emphasis o o smute o o zero detection x o slow roll-off response x o table 8. function list (o: available, x: not available) pdn = l resets the registers to their default values. when the state of p/s pin is changed, the ak4394 should be reset by pdn = l. in serial mode, the internal timing circuit is reset by rstn bit, but the registers are not initialized. cdti cclk c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 csn c1-c0: chip address (fixed to 01) r/w: read/write (fixed to 1, write only) a4-a0: register address d7-d0: control data figure 8. control i/f timing *the ak4394 does not support the read command and chip address. c1/0 and r/w are fixed to 011 *when the ak4394 is in the power down mode (pdn = l) or the mclk is not provided, writing into the control register is inhibited. * for setting the registers, the following sequence is recommended. ? control 1 register (1) writing rstn = 0 and other bits (d6-d1) to the register at the same time. (2) writing rstn = 1 to the register. the other bits are no change. ? control 2 register this writing sequence has no limitation like control 1 register. when setting dem0/1 and smute, rstn is not needed.
asahi kasei [ak4394] m0081-e-00 1999/11 - 19 - n register map addr re g ister name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 cks2 cks1 cks0 dif2 dif1 dif0 rstn 01h control 2 dzfe dzfm slow dfs1 dfs0 dem1 dem0 smute 02h test ga1 ga0 test5 test4 test3 test2 test1 test0 notes: for addresses from 03h to 1fh, data must not be written. when pdn pin goes to l, the registers are initialized to their default values. when rstn bit goes to 0, the only internal timing is reset and the registers are not initialized to their default values. dif0-2, cks1, dfs0 bits are ored with pins respectively. n n n n register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 cks2 cks1 cks0 dif2 dif1 dif0 rstn default 00000001 rstn: internal timing reset 0: reset. all registers are not initialized. 1: normal operation when the states of cks2-0 or dfs1-0 change, the ak4394 should be reset by pdn pin or rstn bit. dif2-0: audio data interface modes (see table 6) initial: 000, mode 0 register bits are ored with dif2-0 pins if p/s = l. cks2-0: master clock frequency select (see table 2) initial: 000, mode 0 cks1 register bit is ored with cks1 pin if p/s = l. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 dzfe dzfm slow dfs1 dfs0 dem1 dem0 smute default 00000000 smute: soft mute enable 0: normal operation 1: dac outputs soft-muted dem1-0: de-emphasis response (see table 7) initial: 00, 44.1khz dfs1-0: sampling speed control (see table 1) 00: normal speed 01: double speed 10: quad speed register bit of dfs0 is ored with dfs0 pin if p/s = l. when changing between normal/double speed mode and quad speed mode, dfs1 bit should be changed after changing mclk frequency. some click noise occurs at that time.
asahi kasei [ak4394] m0081-e-00 1999/11 - 20 - slow: slow roll-off filter enable 0: sharp roll-off filter 1: slow roll-off filter dzfe: data zero detect enable 0: disable 1: enable zero detect function can be disabled by dzfe bit 0. in this case, the dzf pins of both channels are always l. dzfm: data zero detect mode 0: channel separated mode 1: channel anded mode if the dzfm bit is set to 1, the dzf pins of both channels go to h only when the input data at both channels are continuously zeros for 8192 lrck cycles. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h test ga1 ga0 test5 test4 test3 test2 test1 test0 default 00000000 ga1-0: output gain control 00: 0db 01: 2.5db 10: -1db 11: 1.16db test5-0: test mode. do not write any data to d5-0 of 02h.
asahi kasei [ak4394] m0081-e-00 1999/11 - 21 - system design figure 9 and 10 show the system connection diagram. an evaluation board (akd4394) is available which demonstrates the optimum layout, power supply arrangements and measurement results. dvss 1 dvdd 2 mclk 3 pdn 4 bick 5 sdata 6 lrck 7 csn 8 dfs0 9 cclk 10 cdti 11 dif0 12 dzfr 28 cks1 27 dzfl 26 p/s 25 vcom 24 aoutl+ 23 aoutl- 22 aoutr+ 21 aoutr- 20 avss 19 avdd 18 vrefh 17 master clock micro- controller 0.1u 10u + 10u 0.1u + 10u + supply 5v ak4394 0.1u digital supply 5v 13 14 16 15 dif1 dif2 vrefl bvss fs 24bit audio data reset & power down 64fs 10u 0.1u + lch lpf rch lpf rch out lch out analog ground digital ground lch mute rch mute analog figure 9. typical connection diagram (serial mode) notes: - lrck = fs, bick = 64fs. - power lines of avdd and dvdd should be distributed separately from the point with low impedance of regulator etc. - avss, bvss and dvss must be connected to the same analog ground plane. - when aout drives some capacitive load, some resistor should be added in series between aout and capacitive load. - all input pins except pull-down/pull-up pins should not be left floating.
asahi kasei [ak4394] m0081-e-00 1999/11 - 22 - dvss 1 dvdd 2 mclk 3 pdn 4 bick 5 sdata 6 lrck 7 smute 8 dfs0 9 dem0 10 dem1 11 dif0 12 cks2 28 cks1 27 cks0 26 p/s 25 vcom 24 aoutl+ 23 aoutl- 22 aoutr+ 21 aoutr- 20 avss 19 avdd 18 vrefh 17 master clock mode setting 0.1u 10u + 10u 0.1u + 10u + supply 5v ak4394 0.1u digital supply 5v 13 14 16 15 dif1 dif2 vrefl bvss fs 24bit audio data reset & power down 64fs 10u 0.1u + lch lpf rch lpf rch out lch out master clock select analog analog ground digital ground figure 10. typical connection diagram (parallel mode) notes: - lrck = fs, bick = 64fs. - power lines of avdd and dvdd should be distributed separately from the point with low impedance of regulator etc. - avss, bvss and dvss must be connected to the same analog ground plane. - when aout drives some capacitive load, some resistor should be added in series between aout and capacitive load. - all input pins except pull-down/pull-up pins should not be left floating. analog ground digital ground system controller dvss 1 dvdd 2 mclk 3 pdn 4 bick 5 sdata 6 lrck 7 smute 8 dfs 9 dem0 10 dem1 11 dif0 12 cks2 28 cks1 27 cks0 26 p/s 25 vcom 24 aoutl+ 23 aoutl- 22 aoutr+ 21 aoutr- 20 avss 19 avdd 18 vrefh ak4394 17 13 14 16 15 dif1 dif2 vrefr bvss figure 11. ground layout
asahi kasei [ak4394] m0081-e-00 1999/11 - 23 - 1. grounding and power supply decoupling to minimize coupling by digital noise, decoupling capacitors should be connected to avdd and dvdd, respectively. avdd is supplied from analog supply in system and dvdd is supplied from digital supply in system. if avdd and dvdd are supplied separately, the power up sequence is not critical. avss, bvss and dvss must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors for high frequency should be placed as near as possible. 2. voltage reference the differential voltage between vrefh and vrefl set the analog output range. vrefh pin is normally connected to avdd and vrefl pin is normally connected to avss. vrefh and vrefl should be connected with a 0.1f ceramic capacitor. vcom is a signal ground of this chip. an electrolytic capacitor 10f parallel with a 0.1f ceramic capacitor attached to vcom pin eliminates the effects of high frequency noise. no load current may be drawn from vcom pin. all signals, especially clocks, should be kept away from the vrefh, vrefl and vcom pins in order to avoid unwanted coupling into the ak4394. 3. analog outputs the analog outputs are full differential outputs and 2.4vpp (typ@vref=5v) centered around vcom. the differential outputs are summed externally, v aout = (aout+) - (aout-) between aout+ and aout-. if the summing gain is 1, the output range is 4.8vpp (typ@vref=5v). the bias voltage of the external summing circuit is supplied externally. the input data format is 2's complement. the output voltage (v aout ) is a positive full scale for 7fffffh (@24bit) and a negative full scale for 800000h (@24bit). the ideal v aout is 0v for 000000h(@24bit). the internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio passband. figure 12 shows an example of external lpf circuit summing the differential outputs by an op-amp. figure 13 shows an example of differential outputs and lpf circuit example by three op-amps. 1k 1k 1k 1k 1k 1k 1n +vop 1n -vop aout- aout+ 3.3n analog out ak4394 figure 12. external lpf circuit example 1
asahi kasei [ak4394] m0081-e-00 1999/11 - 24 - 300 47u 300 aoutl- 620 10n 300 220 10n 6 4 3 2 7 10u 0.1u 0.1u 10u 10u njm5534d 300 47u 300 aoutl+ 620 10n 300 220 10n 6 4 3 2 7 10u 0.1u 0.1u 10u njm5534d 3 2 1 100 100 0.1u + njm5534d 0.1u 10u 100 4 3 2 4.7n 620 620 430 7 + + + + - + - + + + - + + 4.7n lch -15 +15 6 430 figure 13. external lpf circuit example 2
asahi kasei [ak4394] m0081-e-00 1999/11 - 25 - package 1.0 0.1 0.1 0-10 detail a seating plane note: dimension "*" does not include mold flash. 0.10 0.15-0.05 0.22 0.1 0.65 *9.8 0.2 1.25 0.2 a 1 14 15 28 28pin vsop ( unit: mm ) *5.6 0.2 7.6 0.2 0.5 0.2 +0.1 0.675 n n n n material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
asahi kasei [ak4394] m0081-e-00 1999/11 - 26 - marking akm AK4394VF xxxb yyyyc xxxxbyyyyc data code identifier xxxb: lot number (x : digit number, b : alpha character ) yyyyc: assembly date (y : digit number c : alpha character) important notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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